ARM                53 core/vm-arm.c    ARM(ins, a, b, c >> 8, c)
ARM                55 core/vm-arm.c    ARM(ins, a, 0, b >> 8, b)
ARM                61 core/vm-arm.c    ARM(31, b, a, (b << 3) | 0x3, 0x78); // or rA,rB,rB
ARM                63 core/vm-arm.c    ARM(31, REG(op.a), REG(op.a), 0x0e, 0x70); /* srawi rA,rA,1 */ \
ARM                64 core/vm-arm.c    ARM(31, REG(op.b), REG(op.b), 0x0e, 0x70) /* srawi rB,rB,1 */
ARM                68 core/vm-arm.c    ARM(21, REG(op.a), REG(op.a), 0x08, 0x3c); /* rlwin rA,rA,1,0,30 */ \
ARM                70 core/vm-arm.c    ARM(21, REG(op.b), REG(op.b), 0x08, 0x3c); /* rlwin rB,rB,1,0,30 */ \
ARM                74 core/vm-arm.c    ARM(31, 7 << 2, REG(op.a), REG(op.b) << 3, 0x40); /* cmplw cr7,rA,rB */ \
ARM               191 core/vm-arm.c      ARM(31, REG(op.a), REG(op.a), REG(op.b) << 3 | 0x2, 0x14); // add rA,rA,rB
ARM               198 core/vm-arm.c      ARM(31, REG(op.a), REG(op.b), REG(op.a) << 3, 0x50); // subf rA,rA,rB
ARM               205 core/vm-arm.c      ARM(31, REG(op.a), REG(op.a), REG(op.b) << 3 | 0x1, 0xD6); // mullw rA,rA,rB
ARM               212 core/vm-arm.c      ARM(31, REG(op.a), REG(op.a), REG(op.b) << 3 | 0x3, 0xD6); // divw rA,rA,rB
ARM               219 core/vm-arm.c      ARM(31, REG_TMP, REG(op.a), REG(op.b) << 3 | 0x3, 0xD6); // divw rD,rA,rB
ARM               220 core/vm-arm.c      ARM(31, REG_TMP, REG_TMP, REG(op.b) << 3 | 0x1, 0xD6); // mullw rD,rD,rB
ARM               221 core/vm-arm.c      ARM(31, REG(op.a), REG_TMP, REG(op.a) << 3, 0x50); // subf rA,rD,rA
ARM               230 core/vm-arm.c      ARM(14, REG(op.b), REG(op.b), 0xFF, 0xFF); // addi rD,rD,-1
ARM               231 core/vm-arm.c      ARM(11, 7 << 2, REG(op.b), 0, 0); // cmpwi cr7,rD,0x0
ARM               233 core/vm-arm.c      ARM(31, REG(op.a), REG(op.a), REG_TMP << 3 | 0x1, 0xD6); // mullw rA,rA,rA
ARM               274 core/vm-arm.c      ARM(31, REG(op.a), REG(op.a), REG(op.b) << 3, 0x30); // slw rA,rA,rB
ARM               281 core/vm-arm.c      ARM(31, REG(op.a), REG(op.a), REG(op.b) << 3 | 0x6, 0x30); // sraw rA,rA,rB
ARM               315 core/vm-arm.c    ARM(11, 7 << 2, REG(op.a), 0, PN_FALSE); // cmpwi cr7,rA,0x0
ARM               321 core/vm-arm.c    ARM(11, 7 << 2, REG(op.a), 0, PN_FALSE); // cmpwi cr7,rA,0x0