ARM3               69 core/vm-arm.c    ARM3(24, REG(op.a), REG(op.a), 1); /* ori rA,1 */ \
ARM3               71 core/vm-arm.c    ARM3(24, REG(op.b), REG(op.b), 1); /* ori rB,1 */
ARM3               96 core/vm-arm.c    ARM3(47, 30, 1, 0xFFF8); // stmw r30,-8(r1)
ARM3              101 core/vm-arm.c    ARM3(37, 1, 1, rsp); // stwu r1,-X(r1)
ARM3              137 core/vm-arm.c    ARM3(24, REG(op.a), REG(op.a), val); // ori rA,B
ARM3              145 core/vm-arm.c    ARM3(32, REG(op.a), 30, RBP(op.b)); // lwz rA,-B(rsp)
ARM3              150 core/vm-arm.c    ARM3(36, REG(op.a), 30, RBP(op.b)); // stw rA,-B(rsp)
ARM3              340 core/vm-arm.c    ARM3(32, 1, 1, 0); // lwz r1,(r1)
ARM3              341 core/vm-arm.c    ARM3(46, 30, 1, 0xFFF8); // lmw r30,-8(r1)