REG_TMP           219 core/vm-arm.c      ARM(31, REG_TMP, REG(op.a), REG(op.b) << 3 | 0x3, 0xD6); // divw rD,rA,rB
REG_TMP           220 core/vm-arm.c      ARM(31, REG_TMP, REG_TMP, REG(op.b) << 3 | 0x1, 0xD6); // mullw rD,rD,rB
REG_TMP           221 core/vm-arm.c      ARM(31, REG(op.a), REG_TMP, REG(op.a) << 3, 0x50); // subf rA,rD,rA
REG_TMP           229 core/vm-arm.c      ARM_MOV(REG_TMP, REG(op.a)); // mov rD,rB
REG_TMP           233 core/vm-arm.c      ARM(31, REG(op.a), REG(op.a), REG_TMP << 3 | 0x1, 0xD6); // mullw rA,rA,rA
REG_TMP           218 core/vm-ppc.c      PPC(31, REG_TMP, REG(op.a), REG(op.b) << 3 | 0x3, 0xD6); // divw rD,rA,rB
REG_TMP           219 core/vm-ppc.c      PPC(31, REG_TMP, REG_TMP, REG(op.b) << 3 | 0x1, 0xD6); // mullw rD,rD,rB
REG_TMP           220 core/vm-ppc.c      PPC(31, REG(op.a), REG_TMP, REG(op.a) << 3, 0x50); // subf rA,rD,rA
REG_TMP           228 core/vm-ppc.c      PPC_MOV(REG_TMP, REG(op.a)); // mov rD,rB
REG_TMP           232 core/vm-ppc.c      PPC(31, REG(op.a), REG(op.a), REG_TMP << 3 | 0x1, 0xD6); // mullw rA,rA,rA